Since the beginning of semiconductor manufacturing, photolithography has been recognized as the driving force behind the integrated circuit fabrication process. This trend continues today as the industry strives to pack more devices and the associated circuitry on a chip. As one of the first steps in a lithography process or between deposition processes, a wafer undergoes a preparation process to clean and prepare the wafer surface for a material layer, such as a tri-layer photoresist layer to be coated onto the semiconductor substrate. Wafer surface preparation is critical to achieve a high-yield photolithography process, since many types of defects can be traced back to improperly prepared or contaminated wafers.
A wafer surface is typically prepared by applying a cleaning solvent onto the wafer surface. The manner of dispensing the cleaning solvent varies depending on the application desired. The solvent can be dispensed on the wafer while the wafer is not rotating, known by a process as “static reducing resist consumption (RRC) dispense.” After the static RRC dispense, the wafer is first spun at a low revolutions per minute (rpm) to uniformly spread the solvent. Once the solvent reaches the wafer edge, the rpm are accelerated to a final spin speed. Another approach is to dispense the cleaning solvent on the wafer that is spinning slowly in order to uniformly coat the wafer, followed by acceleration to the final spin speed. This is referred to as a “dynamic RRC dispense.”
Once the solvent has been dispensed onto the wafer surface, a photoresist layer can thereafter be spin coated onto the surface. In both the static RRC and the dynamic RRC dispense approaches, however, the photoresist layer applied onto the wafer surface may exhibit poor coverage, poor coating, or pinholes (very small holes) in the resist. Poor coating or uneven resist coating are undesirable because these wafers can exhibit low yields or fatal defects. Pinholes are microscopically small voids that pass completely through the resist to the substrate material. They are undesirable for subsequent etch processing because the etch chemicals can pass through the small voids and damage the underlying substrate material. These problems are more evident in wafers produced at advanced processing nodes, such as 28 nm and beyond where more device features are packed on the chip.